4.0 OPERATING
V
OVLO
+
V
OVLO
–
1
2
3
5
4
6
Figure 16 –
Timing diagram
v i c o r p o w e r. c o m
C
B
V
IN
NL
V
UVLO
+
V
UVLO
–
PC
5V
3V
3V
5V
2.5 V
C
500mS
before retrial
Vout
G
D
A
E
F
LL • K
I
OUT
I
SSP
I
OCP
H
VIB0002TFJ
TM
3 V @ 27°C
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
0.4 V
Notes:
A: T
ON1
B: T
OVLO*
C: Max recovery time
D:T
UVLO
E: T
ON2
F: T
OCP
G: T
PC–DIS
H: T
SSP**
1: Controller start
2: Controller turn off
3: PC release
4: PC pulled low
5: PC released on output SC
6: SC removed
– Timing and voltage is not to scale
– Error pulse width is load dependent
*Min value switching off
**From detection of error to power train shutdown
PRELIMINARY DATASHEET
Page 11 of 16
Rev. 1.3
9/2009
VICOR [ VICOR CORPORATION ]
