Application Note
The VI-ARM Autoranging Rectifier Module (ARM) provides
an effective solution for the AC front end of a power supply
built with Vicor DC-DC converters. This high performance
power system building block satisfies a broad spectrum of
requirements and agency standards.
The ARM contains all of the power switching and control
circuitry necessary for autoranging rectification, inrush current
limiting, and overvoltage protection. This module also provides
converter enable and status functions for orderly power
up/down control or sequencing. To complete the AC front end
configuration, the user needs only to add holdup capacitors and
a suitable input filter with transient protection.
Functional Description
The switch that bypasses the inrush limiting PTC (positive
temperature coefficient) thermistor is open when power is
applied, as is the switch that engages the strap for voltage
doubling. (See
Fig. 6).
In addition, the converter modules are
disabled via the Enable (EN) line, and Bus-OK (B OK) is high.
Power-Up Sequence.
(See
Fig. 7).:
1.1
Upon application of input power, the output bus capacitors
begin to charge. The thermistor limits the charge current,
and the exponential time constant is determined by the
holdup capacitor value and the thermistor cold resistance.
The slope (dv/dt) of the capacitor voltage approaches
zero as the capacitors become charged to the peak of the
AC line voltage.
2.2
2.1
If the bus voltage is less than 200V as the slope nears
zero, the voltage doubler is activated, and the bus voltage
climbs exponentially to twice the peak line voltage.
If the bus voltage is greater than 200V, the doubler is
not activated.
If the bus voltage is greater than 235V as the slope
approaches zero, the inrush limiting thermistor is
bypassed. Below 235V, the thermistor is not bypassed.
The converters are enabled 50 milliseconds after the
thermistor bypass switch is closed.
Bus-OK is asserted after an additional 50 millisecond
delay to allow the converter outputs to settle within
specification.
3.1
4.1
5.1
Power-Down Sequence.
(See
Fig. 7).
When input power is
turned off or fails, the following sequence occurs as the bus
voltage decays:
1.2
Bus-OK is deasserted when the bus voltage falls below
205Vdc (Typ.).
The converters are disabled when the bus voltage falls
below 200Vdc. If power is reapplied after the converters
are disabled, the entire power-up sequence is repeated. If
a momentary power interruption occurs and power is
reestablished before the bus reaches the disable threshold,
the power-up sequence is not repeated.
+Out
90–132V
AC Line
Strap
Strap
Output
Bus
(Vdc)
–Out
N
EN
Microcontroller
BOK
Strap
PTC
Thermistor
Bypass
Converter
Enable
Bus OK
Power
Up
Power
Down
PTC
Thermistor
L
400
300
200
100
0
1.1
2.1
3.
1
4.1
5.
1
2.2
1.2
50ms
50ms
Figure 6—Functional
block diagram
Vicor Corp.
Tel: 800-735-6200, 978-470-2900 Fax: 978-475-6715
Figure 7—Timing
diagram: power up/down sequence
ARM, Autoranging Rectifier Module
Rev. 2.4
Page 5 of 12
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