PRELIMINARY
Functional Description (continued)
The active loop senses the output current and reduces the
headroom voltage in a linear fashion to approximate
constant power dissipation of MicroRAM with increasing
loads (see Figures 5, 6 & 7, p. 6). The headroom setting
can be reduced to decrease power dissipation where the
transient requirement is low and efficient ripple
attenuation is the primary performance concern.
The active dynamic headroom range is limited on the low
end by the initial headroom setting and the maximum
expected load. If the maximum load in the application is
10 Amps, for example, the 1 Amp headroom can be set
75mV lower to conserve power and still have active
headroom at the maximum load current of 10 Amps. The
high end or maximum headroom range is limited by the
internal OR’ing diode function.
The SC or trim-up function can be used when remote
sensing is not available on the source converter or is not
desirable. It is specifically designed for converters with a
1.23 Volt reference and a 1k ohm input impedance like
Vicor 2nd Generation converters. In comparison to remote
sensing, the SC configuration will have an error in the load
voltage versus load current. It will be proportional to the
output current and the resistance of the load path from the
output of the MicroRAM to the load.
The OR’ing feature prevents current flowing from the
output of the MicroRAM back through it’s input terminal
in a redundant system configuration in the event that a
converter output fails. When the converter output
supplying the MicroRAM droops below the OR’ed output
voltage potential of the redundant system, the input of the
MicroRAM is isolated from it’s output. Less than 50mA
will flow out of the input terminal of the MicroRAM over
the full range of input voltage under this condition.
+In
SC
C
TRAN
–In
Passive
Block
Active
Block
+Out
SC
Control
V
REF
–Out
µRAM
Block Diagram
Application Notes
Load capacitance can affect the overall phase margin of
the MicroRAM active loop as well as the phase margin of
the converter loop. The distributed variables such as
inductance of the load path, the capacitor type and value as
well as its ESR and ESL also affect transient capability at
the load. The following guidelines should be considered
when point of load capacitance is used with the MicroRAM
in order to maintain a minimum of 30 degrees of phase margin.
2) For the case where load capacitance is connected
directly to the output of the MicroRAM, i.e. no
trace inductance, and the ESR is >1 milliohm:
(a) 20µF to 200µF load capacitance needs an ESL
of >50nH
(b) 200µF to 1,000µF load capacitance needs an
ESL of >5nH
3) Adding low ESR capacitance directly at the output
terminals of MicroRAM is not recommended and
may cause stability problems.
4) In practice the distributed board or wire inductance at a
load or on a load board will be sufficient to isolate the
output of the MicroRAM from any load capacitance
and minimize any appreciable effect on phase margin.
1) Using ceramic load capacitance with <1milliohm
ESR and <1nH ESL:
(a) 20µF to 200µF requires 20nH of trace/wire
load path inductance
(b) 200µF to 1,000µF requires 60nH of trace/wire
load path inductance
Vicor Corp.
Tel: 800-735-6200, 978-470-2900 Fax: 978-475-6715
MicroRAM Data Sheet
Rev. 1.1
Page 4 of 8
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