PRELIMINARY
Application Information
V•I Chip Pre-Regulator Module
Vout = V
L
± 2%
I
L
VC
PC
TM
IL
NC
PR
VH
SC
SG
OS
NC
CD
R
OS
R
CD
+In
PRM-AL
Factorized
Bus (V
f
)
0.4
μH
+In
+Out
+Out
Vin
–In
–Out
V
f
=
(I
L
•Ro)
V
L
+
K
K
TM
VC
PC
VTM
K
Ro
-Out
+Out
-In
L
O
A
D
-Out
Figure 14
— Adaptive Loop compensation with soft start using the SC port.
Output Voltage Setting with Adaptive Loop
The equations for calculating R
OS
and R
CD
to set a VTM output
voltage are:
93100
R
OS
=
( V
L
• 0.8395 ) – 1
K
(1)
Where V
fd
is the desired factorized bus and V
fs
is the set factorized bus.
A low voltage source can be applied to the SC port to margin the load
voltage in proportion to the SC reference voltage.
An external capacitor can be added to the SC port as shown in Figure 14 to
control the output voltage slew rate for soft start.
R
CD
=
91238
R
OS
+1
(2)
Nominal Vout
Range (Vdc)
0.8
↔
1.1
↔
1.6
↔
2.2
↔
3.3
↔
4.3
↔
6.5
↔
8.7
↔
13.0
↔
17.4
↔
26.0
↔
1.6
2.2
3.3
4.4
6.6
8.8
13.4
17.9
26.9
36.0
54.0
VTM
K Factor
1/32
1/24
1/16
1/12
1/8
1/6
1/4
1/3
1/2
2/3
1
V
L
= Desired load voltage
V
OUT
= VTM output voltage
K = VTM transformation ratio
(available from appropriate VTM data sheet)
V
f
= PRM output voltage, the Factorized Bus (see Figure 14)
R
O
= VTM output resistance
(available from appropriate VTM data sheet)
I
L
= Load Current
(actual current delivered to the load)
Table 2
— 048 input series VTM K factor selection guide
Output Voltage Trimming (optional)
After setting the output voltage from the procedure above the output
may be margined down (26Vf min) by a resistor from SC-SG using this
formula:
10000 V
fd
V
fs
- V
fd
R
d
Ω
=
vicorpower.com
800-735-6200
V•I Chip Pre-Regulator Module
P048K048T24AL
Rev. 1.4
Page 9 of 15
VICOR [ VICOR CORPORATION ]
