CD-700, VCXO Based PLL
Figure 7. SPICE Model
Vi Ri
E1 R2 C1
E2 R1 C2
Rf
Cf E3 R5 C4
E4 R6 C5 E5
E6
R7
1
2
3
4
5
6
7
8
9
10
11
12
*****CD-700 ac Loop model
vi 1 0 ac 1
ri 1 0 1k
*****Phase Detector
e1 2 0 1 0 1 (for closed loop response use: e1 2 0 1 12 1)
r2 2 3 30k
c1 3 0 60p
*****Phase Detector Gain=0.53 x Data Density (Data Density = 1 for clocks) for 5 volt
operation and = 0.35 x Data Density for 3.3 volt operation
e2 4 0 3 0 .35
*****Loop filter
r1 4 5 60k
c2 5 0 10p
rf 5 6 90k
cf 6 7 1.0u
e3 7 0 5 0 –10000
***** VCXO, Input Bandwidth=50kHz
r5 7 8 160k
c4 8 0 20p
*****VCXO Gain x 2∏ (Example: 19.440 MHz x 100 ppm x 2 x ∏)
e4 9 0 8 0 12214
*****1/S model
r6 9 10 1000
c5 10 11 0.001u
e5 11 0 10 0 –1e6
****Divide by n
e6 12 0 11 0 1
r7 12 0 1k
The bold numbers are user selectable R and C values that will vary depending
on the application (see Figure 11).
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Page 8 of 14
Tel: 1-88-VECTRON-1 • Web: www.vectron.com
Rev : 06Apr08