VL-FS-MGLS128128-19C REV. A
(MGLS128128-HT-HV-LED04)
MAY/2002
PAGE 10 OF 10
4.4 Timing Diagram of VDD Against V0.
Power on sequence shall meet the requirement of Figure 3, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY
VOLTAGE
0V
50ms(typical)
OV
LCD SUPPLY
VOLTAGE
V0
Figure 3: Timing Diagram of VDD Against V0.
“Varitronix Limited reserves the right to change this specification.”
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