US3022
Vref Section
Vref Initial Accuracy
Vref Initial Accuracy
Vref Change with Load
Vref Output Impedance
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
No Load,Ta=25
No Load, Over Temp
No Load to 30K load
1.980
1.960
-2
150
2.000
2.000
300
2.020
2.040
600
V
V
%
Ohm
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
Table 1 - Set point voltage vs. VID codes
PIN DESCRIPTIONS
PIN# PIN SYMBOL
7
VID0
Pin Description
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by
a 27kΩ resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a
27kΩ resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by a
27kΩ resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open,his pin is pulled up internally by
a 27kΩ resistor to 5V supply.
This pin provides a 2V reference that remains on when the 5V pin is connected to the 5V
standby of the ATX supply. In this application, the Vref pin is used to provide reference for
the ACPI regulators.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when Vsen1 pin is more than
10% above the DAC voltage setting.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to vout1 and GND to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from Vout1 to FB1 must be less than 1000Ω.
This pin controls the gate of an external MOSFET for the AGP linear regulator.
This pin controls the gate of an external transistor for the 2.5V Clock linear regulator.
Rev. 1.0
11/2/99
6
VID1
5
VID2
4
VID3
3
Vref
8
PGOOD
21
FB
1
10
Drive2
Drive5
4-4
UNISEM [ UNISEM ]
