VGA-P014458-QGG
17-27GHz Variable Gain Amplifier
Note
Due to ESD protection circuits on RF input and output, an external capacitance might be
requested to isolate the product from external voltage that could be present on the RF
accesses.
12
Vd1, Vd2
24
RFin
RFout
2
17
Gc1
Vg12
Gc2
Gc3
Vg3
8
27
9
14
26
ESD protections are also implemented on gate accesses.
The DC connections do not include any decoupling capacitor in package, therefore it is
mandatory to provide a good external DC decoupling on the PC board, as close as possible
to the package.
Definition of the Sij reference planes
The reference planes are defined from
the footprint of the recommended
characterization board shown to the
right.
The reference is the symmetrical axis of
the package. The input and output
reference planes are located at 3.66mm
offset (input wise and output wise
respectively) from this axis. Then, the
given Sij incorporates this land pattern.
Ref: DSVGA-PO14458-QGG8028 - 28 Jan 08
13/16
/Specifications subject to change without notice
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UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
