0.5-11.5 GHz Divide by 4 prescaler
Typical bias tuning
Vdd
CND2050
1 nF
Signal generator
50 Ohms load
Tansmission lines
are 50 Ohms
0¦
1 nF
180°¦
1
8
1 nF
Spectrum
analyzer
50 Ohms load
1 nF
Vss
Vss
4
5
Fig.1 : Typical measurement and RF biasing configuration with differential inputs
Vdd
Signal generator
50 Ohms load
Tansmission lines
are 50 Ohms
1 nF
1
8
1 nF
Q
F/4 RF output (50 Ohms)
QB
1 nF
Vss
Vss
1 nF
50 Ohms
4
5
Fig.2 : RF biasing configuration with single input and ouput
Vdd
Vdd
Internal divider by 4
CK
CKB
5K
5K
Q
QB
500
Vss
Fig.3 : Chip block diagram
Ref. : DSCND20500257 -13-Sep.-00
7/9
Specifications subject to change without notice
500
Vss
Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE
Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
