CHV2242c
Typical Assembly and Bias Configuration
Q-band VCO
This drawing shows an example of assembly and bias configuration. All the
transistors are internally self-biased. The positive and negative voltages can be
respectively connected together (see drawing) according to the recommended
values given in the electrical characteristics table.
Due to the high value of
frequency sensitivity versus tuning voltage (around 500MHz/V), the signal
applied to V_tune port must have very low level of noise.
For the RF pads the equivalent wire bonding inductance (diameter=25µm) has to
be according to the following recommendation.
Port
ERC1 (11)
ERC2 (1)
RF_out (2)
Equivalent inductance
(nH)
L_erc1 = 0.4
L_erc2 = 0.4
L_out = 0.28
Approximated wire
length (mm)
0.5
0.5
0.35
For a micro-strip configuration a hole in the substrate is recommended for chip
assembly.
Ref. : DSCHV2242c6354 - 20 Dec 06
4/9
Specifications subject to change without notice
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