CHV2240
K-band VCO / Q-band Multiplier
Typical Assembly and Bias Configuration
DC/IF lines
Vt
-V
+V
>= 120pF
>= 120pF
4
5
6
7
8
9
10
11 12 13
14
µ-strip line
3
2
16
15
µ-strip line
L_erc
1
17
L_out
This drawing shows an example of assembly and bias configuration. All
the transistors are internally self biased.
For the RF pads the equivalent wire bonding inductance (diameter=25µm)
have to be according to the following recommendation.
Port
ERC (2)
RF_out (16)
Equivalent inductance
(nH)
L_erc = 0.4
L_out = 0.4
Approximated wire
length (mm)
0.5
0.5
For a micro-strip configuration a hole in the substrate is recommended for chip
assembly.
Ref. :DSCHV22400096 -05-Apr-00
4/8
Specifications subject to change without notice
Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE
Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
