37-40GHz Down Converter
CHR3694-QDG
Notes
The biasing circuits of the stages of the circuit are given in the schemes below.
Vd=4V
1.9k
9
1.9k
100
26
OUT
1.9k
26
Stage 3
Stage 2
Stage 1
Self-biased
60
IN
Self-biased
Self-biased
100
21
Gain control
60
100
150
LNA
Vgc=-2V 0V
Vdx=4V
1.23k
8
42
LO OUT
1.23k
10
Stage Buffer 2
Stage
2 times multiplier
Self-biased
LO IN
Stage Buffer 1
Self-biased
38
57
200
LO
Vgx
1.2k
0.5
0.5
Vgm
Ref. : DSCHR3694-QDG – February 09
15/18
Specifications subject to change without notice
Route Départementale 128, BP46 - 91401 ORSAY Cedex - FRANCE
Tel.: +33 (0) 1 69 33 03 08 - Fax: +33 (0) 1 69 33 03 09
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
