CHK040A-SOA
40W Power Packaged Transistor
Recommended Assembly Procedure
CHK040A-SOA is available has a flange package to be bolt down onto a thermal heat sink
also used as main electrical ground. Use preferably screw M2 and flat washers.
Thermal and electrical resistance at the package to heat sink interface has to be as low as
possible. Thermal electrically conductive grease or conductive thin layer like indium sheets
are recommended between the package and the heat sink.
In case a thermal grease is selected, we recommend to use material offering thermal
conductivity >5W/m.K and electrical resistivity <0.01 ohm.cm. The grease layer thickness
should be about 25µm (1 mil).
Contact interface quality can be improved by cleaning process prior device mounting on the
heat-sink. Such operation will enhance the thermal and electrical contact by oxide removal at
each interface.
Package leads can be soldered on printed circuit board’s traces by using RoHS solder past.
Cavity depth and width to be performed into the heat-sink where the device will be mounted
are important to achieve the best performances. These dimensions have to be optimized in
order to minimize the distance between device and signal traces made on the printed circuit
board (PCB). But they also have to be calculated in order to accommodate device variations
in height. The following drawing gives the relationship between device dimensions (Hpack &
Wpack) and optimal cavity depth (Hcav) and width (Wcav) depending on the printed circuit-
board configuration (HPCB)
Ref. : DSCHK040ASOA3021 - 21 Jan 13
12/14
Specifications subject to change without notice
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Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
