CHE1270-QAG
Definition of the Sij reference planes
5-44GHz Detector
The reference planes used for Sij
measurements given above are symmetrical
from the symmetrical axis of the package
(see drawing beside). The input and output
reference planes are located at 2.65mm
offset (input wise and output wise
respectively) from this axis. Then, the given
Sij parameters incorporate the land pattern of
the evaluation motherboard recommended in
paragraph "Evaluation mother board".
Notes
RF IN
CHE1270
Matching
27kΩ
Ω
Vdet
DC
27kΩ
Ω
Vref
Recommended external resistors assembly
27k resistors in parallel with Vdet and Vref pads are recommended to provide the best
behaviour in the whole operating temperature range.
As the voltage detection is the difference between Vref and Vdet, the external resistor value
should be identical on these two ports.
For information, a variation of 3% leads around 1mV variation of detected voltage.
Due to ESD protection circuits on RF input, an external capacitance might be requested to
isolate the product from external voltage that could be present on the RF access.
ESD protections are also implemented on Vdet and Vref accesses.
The DC connection (on DC pad) does not include any decoupling capacitor in package,
therefore it is mandatory to provide a good external DC decoupling on the PC board, as
close as possible to the package.
Ref. : DSCHE1270-QAG0329 - 25 Nov 10
10/12
Specifications subject to change without notice
Route Départementale 128, BP46 - 91401 ORSAY Cedex - FRANCE
Tel.: +33 (0) 1 69 33 03 08 - Fax: +33 (0) 1 69 33 03 09
UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
