CHA5052-QGG
Note
7- 16GHz High Power Amplifier
Due to ESD protection, RFin and RFout are DC grounded, an external capacitance might
be requested to isolate the product from external voltage that could be present on the RF
accesses.
26
Vd1, 2
5
RFin
23
Vd3
17
RFout
Vg1, 2
9
Vg3 Vd3
11
13
ESD protections are also implemented on gate accesses.
The DC connections do not include any decoupling capacitor in package, therefore it is mandatory
to provide a good external DC decoupling on the PC board, as close as possible to the package.
Definition of the Sij reference planes
The reference planes are defined from the
footprint
of
the
recommended
characterization board shown below under
the number 96402.
The reference is the symmetrical axis of the
package. The input and output reference
planes are located at 3.66mm offset (input
wise and output wise respec.) from this axis.
Then, the given Sij incorporates this land
pattern.
Ref: DSCHA5052QGG7033 - 02 Feb 07
8/10
/Specifications subject to change without notice
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UMS [ UNITED MONOLITHIC SEMICONDUCTORS ]
