10-16GHz Low Noise Amplifier
Typical Chip Assembly
C = 100pF
Vd
CHA2066
IN
OUT
B
E
Chip Biasing options
This chip is self-biased, and flexibility is provided by the access to number of pads. the internal
DC electrical schematic is given in order to use these pads in a safe way.
The two requirements are :
N°1 : Not exceed Vds = 3.5Volt
( internal Drain to Source voltage ).
N°2 : Not biased in such a way that Vgs becomes positive.
( internal Gate to Source voltage )
We propose two standard biasing :
Low Noise and low consumption :
Vd = 4V and B & D grounded.
All the other pads non connected ( NC ).
Idd = 45mA & Pout-1dB = +10dBm Typical.
( Equivalent to A,B,C,D,E : NC and Vd=4V ; G1=+1.4V ; G2=+1.4V).
Low Noise and high output power : Vd = 4V and B & E grounded.
All the other pads non connected ( NC ).
Idd = 55mA & Pout-1dB = +13dBm Typical.
( Equivalent to A,B,C,D,E : NC and Vd=5V ; G1=+1.4V ; G2=+4.0V).
A file is available on request to help the biasing option tuning.
Ref. : DSCHA20664281 - 07 Oct 04
7/8
Specifications subject to change without notice
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