urn3750
Block Diagram
R.C.INPUT - - - - - - -
CPCLK
RID
I
I
ERROR
WD
TIM0
7
i
VLD
MXCLKR
L
COMPARATOR
MXD
Al-Al2
64ms/128ms
TIMER
STATE
CONTROLLER
CLR
INIT
I
VALID 4
COUNTER
T/R OUT
Block
Diagram Description
CLK of Comparator
CPCLK
WXCLKR: CLK of Multiplexer when in Receiver mode
WXCLKT CLK of Multiplexer when in Transmitter mode
Output data of Multiplexer (one of Al, A2 ....
MXD:
RID
VLD.
A12)
Sampled data by Sampling CKT
“Valid” signal. It is used to trigger Valid 4
Counter and reset 64ms/128ms Timer
Clear signal of Comparator
CLR:
Error signal from Comparator
ERROR:
TIMER time-out signal (64ms or 128ms)
TIMO :
T/R OUT: Transmit/Receiver output pin
Reset signal of Valid 4 Counter
INIT:
Word detected signal
WD:
Transmitter output
TXO:
Receiver output
PXO:
2-4
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