QPF7200
2.4GHz Integrated Wi-Fi Front-End Module
Pin Configuration and Description
VCC2
RX
GND
GND
LNA_EN
GND
PA_EN
GND
TX/RX_EN
GND
RFIN
GND
VCC1
ANT
GND
NC
PDET
GND
SW_EN
TX_BAW/BYP
Top View
Pin Number
Label
Description
RF output port for the 802.11 LNA. This port is matched to 50Ω and DC blocked
internally
1
RX
2
GND
PA_EN
GND
RFIN
GND
VCC1
NC
Ground connection.
3
Enable Pin for the PA. May be pulsed for lower duty cycle operation
Ground connection.
4
5
RF input for the TX Chain. This port is matched to 50 Ω and DC blocked internally.
Ground connection.
6
7
Supply Rail for PA, 5V Nominal
8
GND on PCB (not internally connected)
Power Detect Voltage
9
PDET
GND
10
11
12
13
14
15
16
17
18
19
20
Ground connection.
TX_BAW/BYP Path Selection Pin for TX Bypass/ TX Thru BAW
SW_EN
GND
Switch Logic Enable Pin. May be tied to Vcc2 if Voltage < 3.3V
Ground connection
ANT
RF common Port. This port is matched to 50Ω and DC blocked internally
Ground connection
GND
TX/RX_EN
GND
TX/RX Switch Path Selection Pin
Ground connection
LNA_EN
GND
LNA High Gain/Bypass Path Selection Pin
Ground connection
VCC2
Supply Rail for the LNA, and Switches (Limit to 3.3V)
Ground connection. The backside of the package should be connected to the ground
plane through a short path, i.e., PCB vias under the device are recommended.
Pkg Base
Data Sheet 20170719 | Subject to change without notice
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