ML483
0.7 – 1.0 GHz High IP3 Mixer with Integrated LO Amp
Pin Description
LO
1
2
3
4
8
RF
7
GND
6
GND
5
IF
GND
GND
Vcc
Pin
1
2
3
4
5
6
7
8
Symbol
LO
GND
GND
Vcc
IF
GND
GND
RF
Backside Paddle
Description
Local Oscillator (LO) Input. Internally matched to 50
. Internally DC blocked. External
blocking not required.
Ground
Ground
Positive Supply Voltage. Requires capacitive decoupling at pin.
Intermediate Frequency (IF) Output. Internally matched to 50 . No Internal DC blocking.
External blocking cap required if DC present.
Ground
Ground
RF Input. Internally matched to 50 . No Internal DC blocking. External blocking cap
required if DC present.
Ground
Applications Information
PC Board Layout
Top RF layer is .014” FR4, є
r
= 4.3, 4 total layers (0.062”
thick) for mechanical rigidity. Metal layers are 1-oz
copper. Microstrip line details: width = .026”, spacing =
.026”.
The ML483 application board is easy to use requiring only
1 external decoupling cap. This cap should be placed as
close as possible to Vcc pin 4. All three ports use 50
microstrip. There are 5 grounding vias that are not shown.
The backside paddle requires these 5 vias for good RF
grounding. The mechanical configuration diagram on the
next page illustrates proper placement of these vias.
The pad pattern shown has been developed and tested for
optimized assembly at TriQuint Semiconductor. The PCB
land pattern has been developed to accommodate lead and
package tolerances. Since surface mount processes vary
from company to company, careful process development
is recommended.
For
further
technical
www.TriQuint.com
information,
Refer
to
Data Sheet: Rev C 03/23/10
© 2010 TriQuint Semiconductor, Inc.
-
6 of 8
-
Disclaimer: Subject to change without noticee
Connecting the Digital World to the Global Network
®
TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
