AGR09180EF
180 W, 865 MHz—895 MHz, N-Channel E-Mode, Lateral MOSFET
Introduction
The AGR09180EF is a high-voltage, gold-metalized,
laterally diffused metal oxide semiconductor
(LDMOS) RF power transistor suitable for cellular
band, code-division multiple access (CDMA), global
system for mobile communication (GSM), enhanced
data for global evolution (EDGE), and time-division
multiple access (TDMA) single and multicarrier class
AB wireless base station amplifier applications. This
device is manufactured on an advanced LDMOS
technology, offering state-of-the-art performance,
reliability, and thermal resistance. Packaged in an
industry-standard CuW package capable of deliver-
ing a minimum output power of 180 W, it is ideally
suited for today's RF power amplifier applications.
Table 1. Thermal Characteristics
Parameter
Thermal Resistance,
Junction to Case
Sym
R
JC
Value
0.35
Unit
°C/W
Table 2. Absolute Maximum Ratings*
Parameter
Sym Value Unit
Drain-source Voltage
V
DSS
65
Vdc
Gate-source Voltage
V
GS
–0.5, +15 Vdc
Total Dissipation at T
C
= 25 °C P
D
500
W
Derate Above 25
ˇC
—
2.86 W/°C
Operating Junction Tempera-
T
J
200
°C
ture
Storage Temperature Range
T
STG
–65, +150 °C
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress rat-
ings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating*
AGR09180EF
HBM
MM
CDM
Minimum (V)
500
50
1000
Class
1B
A
4
Figure 1. AGR09180EF (flanged) Package
Features
Typical performance ratings are for IS-95 CDMA,
pilot, sync, paging, traffic codes 8—13:
— Output power (P
OUT
): 38 W.
— Power gain: 18.25 dB.
— Efficiency: 27%.
— Adjacent channel power ratio (ACPR) for
30 kHz bandwidth (BW):
(750 kHz offset: –45 dBc)
(1.98 MHz offset: –60 dBc).
— Input return loss: 10 dB.
High-reliability, gold-metalization process.
High gain, efficiency, and linearity.
Integrated ESD protection.
Si LDMOS.
Industry-standard packages.
180 W minimum output power.
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations.
PEAK Devices
Agere
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from elec-
trostatic charge. Reasonable precautions in han-
dling and packaging MOS devices should be
observed.
TRIQUINT [ TRIQUINT SEMICONDUCTOR ]
