Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
TP2350B Pin Description
Pin
5
6
7
9
10
13,17
14,16
27,57
30,31
33,34
36,48
37,47
39,45
40,44
41,43
42
50,51
53,54
59
60
1,2,3,4,8,
11,12,15,
18,19,20,
21,22,23,
24,25,26,
28,29,32,
35,38,46,
49,52,55,
56,58,61,
62,63,64
Function
AGND
V5
OCD1
TSS
OCD2
Y2, Y1
Y2B, Y1B
VBOOT2, VBOOT1
OCS2LP, OCS2LN
OCS2HP, OCS2HN
HO2, HO1
HO2COM, HO1COM
LO2COM, LO1COM
LO2, LO1
VN10
VNN
OCS1HN, OCS1HP
OCS1LN ,OCS1LP
SW-FB
SMPSO
NC
Description
Analog ground.
5V power supply input.
Over-current threshold output (Channel 1)
This a test pin for the TP2350B. This pin should be left floating.
Over-current threshold output (Channel 2)
Non-inverted switching modulator inputs
Inverted switching modulator inputs
Bootstrapped voltage to supply drive to gate of high-side FET
(Channel 2 & 1)
Over Current Sense inputs, Channel 2 low-side
Over Current Sense inputs, Channel 2 high-side
High side gate drive output (Channel 2 & 1)
Kelvin connection to source of high-side transistor (Channel 2 & 1)
Kelvin connection to source of low-side transistor (Channel 2 & 1)
Low side gate drive output (Channel 2 & 1)
“Floating” supply input for the FET drive circuitry. This voltage must be stable
and referenced to VNN.
Negative supply voltage.
Over Current Sense inputs, Channel 1 high-side
Over Current Sense inputs, Channel 1 low-side
Feedback for regulating switching power supply output for VN10
Switching power supply output for VN10
Not connected (bonded) internally. Leave these pins floating.
Please note that the heatslug on the bottom of the package is connected to VNN.
9 of 9
TK2350, Rev 1.5/09.03
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