Tripath Technology, Inc. – Preliminary Technical Information
Switching Characteristics
TA = 25 °C. Unless otherwise specified, VA50 = 5.0V, VD33 = 3.3V, VA33 = 3.3V.
SYMBOL
PARAMETER
Master Clock Timing
CONDITIONS
MIN
TYP
MAX
UNITS
fMCK0
dMCK0
fMCK1
dMCK
Frequency
Duty Cycle
Frequency
Duty Cycle
HFR bit = 0
HFR bit = 0
HFR bit = 1
HFR bit = 1
8.192
TBD
16.384
TBD
12.288
TBD
24.576
TBD
MHz
%
MHz
%
I2S Control Interface Timing
BITCK Pulse Width Low
BITCK Pulse Width High
DATA Setup Time
DATA Hold Time
I2C Control Interface Timing
SCK Frequency
SCK Pulse Width Low
SCK Pulse Width High
SDA Setup Time
SDA Hold Time
See section titled "Digital
Input Format".
dBITCKL
tBITCKH
tDATAset
tDATAhold
TBD
TBD
TBD
TBD
ns
ns
ns
ns
fSCK
tSCKL
tSCKH
tSDAset
tSDAhold
tSDA rise
tSDAfall
0
400
KHz
us
us
ns
ns
1.3
0.6
100
90
SDA Rise Time
SDA Fall Time
300
300
ns
ns
5
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
