Tri path Technol og y, I nc. - Techni cal I nformati on
Pin Description
PIN
1
2
3
4
5
6
NAME
/
FUNCTION
IN1
IN2
IN3
IN4
BIASCAP
SLEEPB
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT (L)
DESCRIPTION
Channel 1 Input
Channel 2 Input
Channel 3 Input
Channel 4 Input
Internal reference bypass capacitor connection
Logic input, ACTIVE LOW. Setting SLEEP to low puts the
TAA4100A in sleep mode. This pin must be driven high via an
external power supply or microcontroller for the TAA4100A to
begin operation. Input range is 0 to 5V with 3.3V compliant
inputs.
Logic input, ACTIVE HIGH. Enables Analog Mode operation.
Typically driven by an external power supply of microcontroller.
Input range is 0 to 5V with 3.3V compliant inputs.
Logic output, ACTIVE LOW. OVRLDB low indicates the input
has overloaded the amplifier
Logic Input, ACTIVE LOW. Setting MUTE to low puts the device
in mute mode. Typically driven by external power supply or
microcontroller. Input range is 0 to 5V with 3.3V compliant
inputs.
Analog ground
On chip 5V regulator bypass capacitor connection
Logic output, ACTIVE LOW. HMUTEB low indicates TAA4100A
is in mute mode
Positive power supply voltage connection
Analog ground
Charge pump output capacitor
Positive Output Channel 4
Positive Supply Voltage Channel 4
Power Ground
Negative Output Channel 4
Negative Output Channel 3
Positive Supply Voltage Channel 3
Positive Output Channel 3
Open Drain Logic Output, ACTIVE HIGH. FAULT high indicates
fault condition.
Positive Output Channel 2
Positive Supply Voltage Channel 2
Negative Output Channel 2
Negative Output Channel 1
Power Ground
Positive Supply Voltage Channel 1
Positive Output Channel 1
External Charge Pump Circuit Output. DCAP is a free running
400kHz square wave between VDDA (pin 13) and AGND (pin
14) with a 14.4Vpp nominal amplitude.
Power Ground
7
8
9
AM
OVRLDB
MUTEB
INPUT (L)
OUTPUT (L)
INPUT (L)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND1
5VGEN
HMUTEB
VPPA
AGND2
CPUMP
OUT4P
VPP4
PGND
OUT4N
OUT3N
VPP3
OUT3P
FAULT
OUT2P
VPP2
OUT2N
OUT1N
PGND
VPP1
OUT1P
DCAP
PGND
GND
OUTPUT (L)
POWER
GND
OUTPUT
OUTPUT
POWER
GND
OUTPUT
OUTPUT
POWER
OUTPUT
OUTPUT (L)
OUTPUT
POWER
OUTPUT
OUTPUT
GND
POWER
OUTPUT
OUTPUT
GND
6
TAA4100A – KL/ Rev. 1.0/11.05