Tripath Technology, Inc. - Technical Information
The above layout shows ideal component placement and routing for supply decoupling. C2 and
C3 are .1uF surface mount capacitors placed directly across their respective VDD and PGND
pins. C1 is a low ESR bulk capacitance electrolytic (at least 100uF). C1’s VDD pin is routed to the
TAA2008’s VDD1 and VDD2 pins on the opposite side of the PCB as the TAA2008. Vias return
the supply trace to the TAA2008 side of the PCB at the VDD1 and VDD2 pins. This arrangement
allows C1’s PGND pin to have a low impedance return path to PGND1 and PGND2 through the
PCB’s ground plane and allows the output traces (OUTM1, OUTP1, OUTM2, AND OUTP2) to be
routed directly to the low pass filter. By having C1’s supply pins directly across the TAA2008’s
VDD and PGND pins supply overshoots will be controlled and mean supply elevation will be
reduced. Effectively decoupling VDD will shunt any power supply trace length inductance.
The construction of the bulk electrolytic is critical. This capacitor should be a low ESR, ripple
rated SMT, or through-hole component. Water based through-hole electrolytic capacitors offer
very cost competitive solutions with extremely low impedance (ESR). These include Nichicon HE
series and Panasonic FM series. Qualified SMT electrolytics include Nichicon UD series and
Panasonic FK series. Panasonic FC capacitors also work well but are likely more costly with no
improvement in performance over the capacitor families mentioned above.
The output L1 – L4 should be placed close to the TAA2008 without compromising the locations of
the closely placed supply decoupling capacitors. The purpose of placing the inductors close to the
TAA2008 output pins in to reduce the trace length of the switching outputs. This will aid in
reducing radiated emissions.
For VDD voltages above 13.2V, or on designs where a tight layout cannot be adhered to due to
physical constraints, it is strongly recommended that the value of CSW is increased to 220uF and
that both low and high side schottky diodes are implemented. These changes will ensure that the
output over shoots will not exceed the absolute maximum rating of 16V. The output diodes, DO,
should be located as close to the output pins as possible and returned to their respective PGND
or VDD, as shown in the Application / Test Diagram.
Please see the External Component Description section on page 6 for more details on the above-
mentioned components. The Application/ Test Circuit refers to both supply decoupling capacitors
as CSW, and the output diodes as DO.
T AA2 0 0 8 Amp l i f i e r Gai n
The ideal gain of the TAA2008 is set by the ratio of two external resistors, RI and RF, and is given
by the following formula:
VO
VI
R F
R I
= −12
where VI is the input signal level and VO is the differential output signal level across the speaker.
Please note that VO is 180° out of phase with VI.
10
TAA2008 –KLi/1.0/05.06
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
