TECHNICAL INFORMATION
Pin Description
Pin
2, 8
3, 7,
16
4
6
9, 12
10, 13
11
14
17
18
19, 28
20
21, 23,
26, 24
22, 25
1, 5, 15
27
29
30
31, 32
Function
V5D, V5A
AGND1, AGND2,
AGND3
REF
OVERLOADB
VP1, VP2
IN1, IN2
MUTE
BIASCAP
SLEEP
FAULT
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD1
NC
VDDA
CPUMP
5VGEN
DCAP2, DCAP1
Description
Digital 5VDC, Analog 5VDC
Analog Ground
B
Internal reference voltage; approximately 1.0VDC
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. Ground if not used.
Input stage bias voltage (approximately 2.4VDC).
When set to logic high, device goes into low power mode. If not used this pin
should be grounded.
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Ground (high current)
Digital Ground
Bridged outputs
Supply pin for high current H-bridges, nominally 13.5VDC.
Not connected
Analog 13.5VDC
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 2 & 8).
Charge pump switching pins. DCAP1 (pin 32) is a free running 300kHz square
wave between VDDA and DGND (13.5Vpp nominal). DCAP2 (pin 31) is level
shifted 10 volts above DCAP1 (pin 32) with the same amplitude (13.5Vpp
nominal), frequency, and phase as DCAP1.
32-pin SSIP Package
(Front View)
NC
V5D
AGND1
REF
NC
OVERLOADB
AGND2
V5A
VP1
IN1
MUTE
VP2
IN2
BIASCAP
NC
AGND3
SLEEP
FAULT
PGND2
DGND
OUTP2
VDD2
OUTM2
OUTM1
VDD1
OUTP1
VDDA
PGND1
CPUMP
5VGEN
DCAP2
DCAP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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TA2020-020, Rev. 4.0, 09.00
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
