TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.5 SII EEPROM MFC IO Crossbar Mapping
The TMC8462 contains a full crossbar.
The 24 MFC IO pins (16x Low Voltage 3.3V MFC IO pins and 8x High Voltage MFC IO pins) of the TMC8462
can be freely assigned to any signal coming from or going to the MFC IO functional blocks.
Without initialization from the SII EEPROM on power up or later via PDI SPI/ECAT memory access during
operation, all IOs are tri-stated.
Note
Certain output signals (e.g. PWM signals, DAC, ...) generate very short pulses
(down to 10ns) which are faster than the slew rate of the HVIO output drivers.
It is still possible to use this configuration, so that the user can evaluate if the
application specific conditions allow to work directly with the HVIO outputs.
Otherwise external signal conditioning is required.
One output signal can be mapped to multiple IO pins, for example to combine the driver strength of
multiple pins. The configuration also allows a mapping of multiple pins to one input signal, but usually
there is no reason for this configuration. When multiple pins are mapped to the same input signal, a logical
OR operation is applied to all input pins.
Each IO pin has a dedicated configuration byte in the SII EEPROM and in the ESC’s memory space within
the ESC Parameter RAM to select the functional MFC IO block signal connected to the physical IO pin:
• MFCIO00 to MFCIO15: SII EEPROM 0084h to 0093h / ESC Parameter RAM from 0580h to 058Fh
2
• MFC_HV0 to MFC_HV7 : SII EEPROM: 0094h to 009Bh / ESC Parameter RAM from 0590h to 0597h
An overview over all configurable MFC IO block signals is given in Table 190.
Name
Function block Description
Direction Value dec. Value
hex.
ZERO
LOW
HGH
TRI
A
none
Disabled
-
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
none
Static LOW output
Static HIGH output
Static tristate (Z) output
ABN_A signal
output
output
-
1
none
2
none
3
ABN decoder
ABN decoder
ABN decoder
ABN decoder
ABN decoder
ABN decoder
SPI
input
input
input
4
An
ABN_An signal (for differential inputs)
ABN_B signal
5
B
6
Bn
ABN_Bn signal (for differential inputs) input
ABN_N signal input
ABN_Nn signal (for differential inputs) input
7
N
8
Nn
9
SCK
SDI
SDO
CS0
SPI SCK signal
SPI SDI signal
SPI SDO signal
SPI CS0 signal
output
input
10
11
12
13
SPI
SPI
output
output
SPI
2
MFC_HV0 to MFC_HV7 ≡ MFCIO16 to MFCIO23
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