TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.3.8 IRQ Control Block
7.3.8.1 Register 51 – MFCIO_IRQ_CFG
Bit
0
Description
ECAT
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
PDI
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
Range [Unit]
ABN encoder unit N-channel event
SD_CH0 target reached event
SD_CH1 target reached event
SD_CH2 target reached event
SD_CH0 compare value event
SD_CH1 compare value event
SD_CH2 compare value event
SPI new data available event
I2C new data available event
I2C transmit complete event
1
2
3
4
5
6
7
8
9
10
I2C new data available event OR I2C transmit -/w
complete event
11
12
13
14
15
16
17
18
19
Watchdog Timeout event
PWM zero pulse event
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
PWM center pulse event
PWM A pulse event
PWM B pulse event
HV_OT_FLAG has been set
BVOUT_OT_FLAG has been set
BVOUT_SC_FL has been set
B3V3_SC_FLAG has been set
22:20 unused/reserved
23
emergency input pin MFC_NES event
Table 176: MFC IO Register 51 – MFCIO_IRQ_CFG
Note
This register is used for masking / enabling the different IRQ sources, which are
or-ed together to set the common MFCIO_IRQ output signal. The MFCIO_IRQ is a
dedicated package pin of TMC8462, which can be connected to a local application
controller.
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