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TMC5161 参数 Datasheet PDF下载

TMC5161图片预览
型号: TMC5161
PDF下载: 下载PDF文件 查看货源
内容描述: [Compact, low power-dissipation Driver & Controller for two-phase stepper motors.]
分类和应用:
文件页数/大小: 129 页 / 2715 K
品牌: TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
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TMC5161 DATASHEET (Rev. 1.01 / 2018-NOV-20)  
92  
15.3 microPlyer and Stand Still Detection  
For each active edge on STEP, microPlyer produces microsteps at 256x resolution, as shown in Figure  
15.2. It interpolates the time in between of two step impulses at the step input based on the last  
step interval. This way, from 2 microsteps (128 microstep to 256 microstep interpolation) up to 256  
microsteps (full step input to 256 microsteps) are driven for a single step pulse.  
Enable microPlyer by setting the intpol bit in the CHOPCONF register.  
GCONF.faststandstill allows reduction of standstill detection time to 2^18 clocks (~20ms)  
The step rate for the interpolated 2 to 256 microsteps is determined by measuring the time interval of  
the previous step period and dividing it into up to 256 equal parts. The maximum time between two  
microsteps corresponds to 220 (roughly one million system clock cycles), for an even distribution of  
256 microsteps. At 12 MHz system clock frequency, this results in a minimum step input frequency of  
12 Hz for microPlyer operation (50 Hz with faststandstill = 1). A lower step rate causes the STST bit to  
be set, which indicates a standstill event. At that frequency, microsteps occur at a rate of (system  
clock frequency)/216 ~ 256 Hz. When a stand still is detected, the driver automatically switches the  
motor to holding current IHOLD.  
Hint  
microPlyer only works perfectly with a stable STEP frequency. Do not use the dedge option if the STEP  
signal does not have a 50% duty cycle.  
STEP  
Interpolated  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66  
microstep  
Motor  
angle  
2^20 tCLK  
STANDSTILL  
(stst) active  
Figure 15.2 microPlyer microstep interpolation with rising STEP frequency (Example: 16 to 256)  
In Figure 15.2, the first STEP cycle is long enough to set the standstill bit stst. This bit is cleared on  
the next STEP active edge. Then, the external STEP frequency increases. After one cycle at the higher  
rate microPlyer adapts the interpolated microstep rate to the higher frequency. During the last cycle at  
the slower rate, microPlyer did not generate all 16 microsteps, so there is a small jump in motor  
angle between the first and second cycles at the higher rate. With the flag GCONF.faststandstill  
enabled, standstill detection is after 2^18 clocks (rather than 2^20 clocks) without step pulse. This  
allows faster current reduction for energy saving in drives with short stand still times.  
www.trinamic.com  
 
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