TMC5161 DATASHEET (Rev. 1.01 / 2018-NOV-20)
23
5.1.2 Read Access
UART READ ACCESS REQUEST DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
RW + 7 bit register
sync + reserved
8 bit slave address
8…15
CRC
24…31
CRC
address
16…23
0...7
Reserved (don’t cares
but included in CRC)
1
0
1
0
SLAVEADDR
register address
0
The read access request datagram structure is identical to the write access datagram structure, but
uses a lower number of user bits. Its function is the addressing of the slave and the transmission of
the desired register address for the read access. The TMC5161 responds with the same baud rate as
the master uses for the read request.
In order to ensure a clean bus transition from the master to the slave, the TMC5161 does not
immediately send the reply to a read access, but it uses a programmable delay time after which the
first reply byte becomes sent following a read request. This delay time can be set in multiples of
eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the
master. In a multi-slave system, set SENDDELAY to min. 2 for all slaves. Otherwise a non-addressed
slaves might detect a transmission error upon read access to a different slave.
UART READ ACCESS REPLY DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
0 ...... 63
8 bit slave
address
8…15
RW + 7 bit
register addr.
16…23
sync + reserved
32 bit data
CRC
56…63
CRC
0…7
24…55
data bytes 3, 2, 1, 0
(high to low byte)
register
1
0
1
0
reserved (0)
0xFF
0
address
The read response is sent to the master using address code %1111. The transmitter becomes switched
inactive four bit times after the last bit is sent.
Address %11111111 is reserved for read accesses going to the master. A slave cannot use this
address.
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