TMC5160 DATASHEET (Rev. 1.08 / 2018-NOV-19)
44
6.4 Encoder Registers
ENCODER REGISTER SET (0X38…0X3C)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
Encoder configuration and use of N channel
See separate table!
Actual encoder position (signed)
RW
0x38
11 ENCMODE
32 X_ENC
-2^31…
+(2^31)-1
binary:
± [µsteps/2^16]
±(0 …
RW
W
0x39
0x3A
Accumulation constant (signed)
16 bit integer part, 16 bit fractional part
X_ENC accumulates
+/- ENC_CONST / (2^16*X_ENC) (binary)
or
32767.999847)
decimal:
32 ENC_CONST
±(0.0 …
32767.9999)
+/-ENC_CONST / (10^4*X_ENC) (decimal)
reset default =
ENCMODE bit enc_sel_decimal switches 1.0 (=65536)
between decimal and binary setting.
Use the sign, to match rotation direction!
Encoder status information
bit 0: n_event
bit 1: deviation_warn
1: Event detected.
R+
WC
To clear the status bit, write with a 1 bit at
the corresponding position.
0x3B
2
ENC_STATUS
Deviation_warn cannot be cleared while a
warning still persists. Set ENC_DEVIATION
zero to disable.
Both bits are ORed to the interrupt output
signal.
Encoder position X_ENC latched on N event
R
0x3C
0x3D
32 ENC_LATCH
Maximum number of steps deviation
between encoder counter and XACTUAL for
deviation warning
ENC_
20
W
DEVIATION
Result in flag ENC_STATUS.deviation_warn
0=Function is off.
www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
