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TMC4670 Datasheet PRELIMINARY • IC Version V0.99 | Document Revision V0.91 • 2016-Nov-09
The ADC engine interfaces integrated ADC channels and maps raw ADC values to signed 16 bit (s16) values
for the inner FOC current control loop based on programmable offset and scaling factors. The FOC torque
PI controller forms the inner base component including required transformations (Clark, Park, inverse
Park, inverse Clark). All functional blocks are pure hardware.
3.2 Communication Interface
The TMC4670 is equipped with an SPI interface for access to all registers of the TMC4670.
3.2.1 SPI Slave User Interface
The SPI of the TMC4670 for the user application has an easy command and control structure. The TMC4670
user SPI acts as a slave. The SPI datagram length is 40 bit with up to 2Mbit/s. The MSB (bit#39) is sent
first. The LSB (bit#0) is sent last. The MSB (bit#39) is the WRITE_notREAD (WRnRD) bit. The bits (bit#39 to
bit#32) are the address bits (ADDR). Bits (bit#31) to (bit#0) are (up to) 32 data bits. The SPI of the TMC4670
immediately responses within the actual SPI datagram on read and write for ease-of-use communication.
Figure 3: SPI Timing
SPI Interface Timing
Characteristics, fCLK = 25MHz
Symbol Condition Min Typ Max Unit
Parameter
SCK valid before or after change of nSCS
nSCS high time
tCC
tCSH
tCSL
tCH
250
250
250
250
250
250
ns
ns
nSCS low time
ns
SCK high time
ns
SCK low time
tCL
ns
SCK low time
tCL
ns
SCK frequency
fSCK
tDU
tDH
tDO
2
MHz
ns
MOSI setup time before rising edge of SCK
MOSI hold time after falling edge of SCK
MISO data valid time after falling edge of SCK
250
250
ns
10
ns
Table 2: SPI Timing Parameter
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