TMC262 DATASHEET (Rev. 2.07 / 2013-FEB-14)
17
AC-Characteristics
clock period is tCLK
SPI Interface Timing
Parameter
Symbol Conditions
Min
Typ
Max
Unit
SCK valid before or after change
of CSN
CSN high time
tCC
10
ns
*)Min time is for
synchronous CLK
with SCK high one
>2tCLK
+10
tCSH
tCLK
ns
t before CSN high
CH
only
SCK low time
SCK high time
*)Min time is for
synchronous CLK
only
tCL
tCLK
>tCLK+10
>tCLK+10
ns
ns
*)Min time is for
synchronous CLK
only
tCH
tCLK
Assumes minimum
OSC frequency
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
fSCK
fSCK
tDU
4
8
MHz
MHz
ns
Assumes
synchronous CLK
10
10
tDH
ns
No capacitive load
on SDO
Data out valid time after falling
SCK clock edge
SDI, SCK, and CSN filter delay
time
tDO
tFILT
tFILT+5
30
ns
Rising and falling
edge
12
20
ns
6.3 Bus Architecture
SPI slaves can be chained and used with a single chip select line. If slaves are chained, they behave
like a long shift register. For example, a chain of two motor drivers requires 40 bits to be sent. The
last bits shifted to each register in the chain are loaded into an internal register on the rising edge of
the CSN input. For example, 24 or 32 bits can be sent to a single motor driver, but it latches just the
last 20 bits received before CSN goes high.
Mechanical Feedback
or virtual stop switch
+VM
Real time Step/Dir
3 x REF_L, REF_R
TMC262
r
interface
e
v
i
r
D
r
VCC_IO
STEP
o
TMC429
t
o
l
Gate driver
Gate Driver
HS
M
o
r
t
S1 (SDO_S)
triple stepper motor
controller
n
Reference switch
processing
o
c
N
n
o
i
D1 (SCK_S)
S2 (nSCS_S)
D2 (SDI_S)
S3 (nSCS_2)
D3 (nSCS_3)
t
S
o
M
Sine Table
4*256 entry
x
Chopper
DIR
Output select
SPI or
Step & Dir
BM
nSCS_C
SCK_C
SDI_C
Driver 2
Driver 3
Step &
Direction
pulse
Gate driver
Gate Driver
2 Phase
Stepper
SPI to master
3x linear RAMP
generator
generation
SDOZ_C
CSN
SCK
SDI
SDO
LS
coolStep™
SPI control,
Config & Diags
RS
nINT
CLK
Interrupt
controller
Position
comparator
Serial driver
interface
2 x Current
Comparator
RS
RS
Microstep
table
2 x DAC
Protection
& Diagnostics
stallGuard2™
POSCOMP
SG_TST
Realtime event trigger
Virtual stop switch
Second driver and motor
Third driver and motor
Motion command
Configuration and
diagnostics SPI(TM)
SPI(TM)
User CPU
l
o
r
t
System interfacing
n
o
c
m
e
t
s
y
S
Figure 6.2 Interfaces to a TMC429 motion controller chip and a TMC262 motor driver
www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
