TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
48
12 Step/Dir Interface
The STEP and DIR inputs provide a simple, standard interface compatible with many existing motion
controllers. The microPlyer STEP pulse interpolator brings the smooth motor operation of high-
resolution microstepping to applications originally designed for coarser stepping. The current settings
are configured separately for motor run and standstill in register IHOLD_IRUN.
12.1 Timing
Figure 12.1 shows the timing parameters for the STEP and DIR signals, and the table below gives
their specifications. When the DEDGE mode bit in the DRVCTRL register is set, both edges of STEP are
active. If DEDGE is cleared, only rising edges are active. STEP and DIR are sampled and synchronized
to the system clock. An internal analog filter removes glitches on the signals, such as those caused by
long PCB traces. If the signal source is far from the chip, and especially if the signals are carried on
cables, the signals should be filtered or differentially transmitted.
+VCC_IO
DIR
SchmittTrigger
tSH
tSL
tDSH
tDSU
STEP
or DIR
Input
250k
0.56 VCC_IO
0.44 VCC_IO
STEP
Internal
Signal
0.26pF
Input filter
R*C = 65ns +-30%
Figure 12.1 STEP and DIR timing, Input pin filter
STEP and DIR interface timing
Parameter
AC-Characteristics
clock period is tCLK
Symbol Conditions
Min
Typ
Max
Unit
step frequency (at maximum
microstep resolution)
fSTEP
dedge=0
½ fCLK
dedge=1
¼ fCLK
fullstep frequency
STEP input low time *)
fFS
tSL
fCLK/512
max(tFILTSD
tCLK+20)
max(tFILTSD
tCLK+20)
,
,
ns
ns
STEP input high time *)
tSH
DIR to STEP setup time
DIR after STEP hold time
STEP and DIR spike filtering time
*)
tDSU
tDSH
tFILTSD
20
20
36
ns
ns
ns
rising and falling
edge
60
85
STEP and DIR sampling relative
to rising CLK input
tSDCLKHI
before rising edge
of CLK input
tFILTSD
ns
*) These values are valid with full input logic level swing, only. Asymmetric logic levels will increase
filtering delay tFILTSD, due to an internal input RC filter.
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