TS8GSSD25S-S
TS16GSSD25S-S/M
TS32GSSD25S-S/M
TS64GSSD25S-S/M
TS128GSSD25S-M
TS192GSSD25S-M
2.5” Solid State Disk
Power on sequence timing diagram
The following timing diagrams and descriptions are provided for clarity and are informative.
Figure 7 : power on sequence
Description:
1. Host/device power-off - Host and device power-off.
2. Power is applied - Host side signal conditioning pulls TX and RX pairs to neutral state (common mode voltage).
3. Host issues COMRESET
4. Host releases COMRESET. Once the power-on reset is released, the host releases the COMRESET signal and puts
the bus in a quiescent condition.
5. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is
also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT.
6. Host calibrates and issues a COMWAKE.
7. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).
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