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TS7887B 参数 Datasheet PDF下载

TS7887B图片预览
型号: TS7887B
PDF下载: 下载PDF文件 查看货源
内容描述: 微功耗,双通道, 125 ksps的,串行输出的12位SAR ADC [A Micropower, 2-channel, 125-ksps, Serial-Output 12-bit SAR ADC]
分类和应用:
文件页数/大小: 20 页 / 1374 K
品牌: TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
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TSA7887  
TSA7887 CONTROL REGISTER DESCRIPTION  
The TSA7887’s write-only control register is 8-bits  
wide. Serial ADC configuration data is uploaded  
from the host processor at the TSA7887’s DIN pin  
on low-to-high SCLK transitions. Serial input data is  
uploaded to the TSA7887 simultaneously as the  
conversion result is transferred out of the TSA7887.  
All serial data transfers require 16 serial clocks  
serial data available on the first eight low-to-high  
SCLK transitions is transferred into the control  
register. The first bit in the serial data stream is  
always interpreted as the MSB. Upon initial power-  
up, the TSA7887’s default control register bit is  
cleared to all zeros (all 0s). Table 1 lists the  
functions of the Control Register’s 8 bits.  
transitions. After a high-to-low CS transition signal,  
Table 1. TSA7887’s 8-Bit Control Register Content Description  
DB7 (MSB)  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1 DB0 (LSB)  
DONTC  
ZERO REF SIN/DUAL  
CH  
ZERO PM1  
PM0  
DBx  
Label  
Comment  
7
DONTC  
Control Register DB7: Bit status of DB7 is “Don’t Care.” In other words, the DB7 bit can be a “0or a “1.  
Control Register DB6: To ensure correct TS7887 operation, Control Register DB6 status must always be a “zero”  
(“0”).  
6
ZERO  
Control Register DB5 Internal Voltage Reference Configuration: The status of DB5 determines whether the  
TSA7887’s internal voltage reference is enabled or disabled. A “0” in the DB5 location will enable the TSA7887’s  
internal voltage reference (default condition). To disable the TSA7887’s internal voltage reference, a “1” must be  
written into DB5’s register location.  
5
REF  
Control Register DB4 - Single-Channel/Dual-Channel Configuration. Control Register DB4 configures the TSA7887 as  
a single-channel or two-channel ADC. Loading a “zero” (“0”) into this register location configures the TSA7887 for  
single-channel operation with the AIN1/VREF pin configured to for internal VREF operation (default configuration). In  
this case, the analog input signal range is 0V to VREF. Loading a “one” (“1”) into this register location configures the  
TSA7887 for two-channel operation with the AIN1/VREF pin configured to its AIN1 function as the second analog  
input. In addition, the conversion process’s reference voltage is internally connected to VDD. In this case, the analog  
input signal range is 0V to VDD. To obtain best performance from the TSA7887 in two-channel operation, the ADC’s  
internal reference should be disabled; that is, a “1” should be loaded into DB5’s register location.  
4
SIN/DUAL  
Control Register DB3 - Channel Select Bit: The bit status of DB3 determines on which channel the TSA7887 is  
converting. When the ADC is configured for dual-channel operation, DB3 determines which channel is converted on  
the next conversion cycle. When DB3 is a zero(a “0”), the AIN0 input is selected and, when DB3 is a one(a “1”),  
the AIN1 input is selected. DB3 should be a “zero” (“0”) when the TSA7887 is configured for single-channel operation.  
3
2
CH  
Control Register DB2: To ensure correct TS7887 operation, Control Register DB2 status must always be a “zero”  
(“0”).  
ZERO  
1
0
PM1  
PM0  
Control Register DB1 and DB0 - Power Management Operating Modes: DB1 and DB0 are decoded to configure the  
TSA7887 into one of four operating modes as shown in Table 2.  
Table 2. TSA7887’s Power Management Operating Modes  
PM1  
PM0  
Mode  
PM Mode 1: In this operating mode, the TSA7887’s power-down mode is enabled if its CS input is a one( a “1”) and is  
operating in full-power mode when its CS input is a zero(a “0”). Thus, the TSA7887 is powered down on a low-to-high  
CS transition and is powered up on a high-to-low CS transition.  
0
0
PM Mode 2: In this operating mode and regardless of the status of any of the logic inputs, the TSA7887 is always fully  
powered up.  
0
1
1
0
PM Mode 3: In this operating mode, the TSA7887 is automatically powered down at the end of each conversion  
regardless of the state of the CS input. ADC wake-up time from full shutdown is 5μs and system design should ensure  
that at least 5μs have elapsed before attempting to perform a conversion in this mode; otherwise, an invalid conversion  
result may occur.  
PM Mode 4: In this operating mode, the TSA7887 is configured for standby operation after conversion. Sections of the  
TSA7887 are powered down; however, the internal 2.5-V reference voltage remains powered up. While PM Mode 4 is  
similar to PM Mode 3, PM Mode 4 operation allows the TSA7887 to power up much faster. For optimal performance, the  
Control Register’s REF bit (DB5) should be a “zero” (“0”) to ensure the internal reference is enabled/remains enabled.  
1
1
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TSA7887DS r1p0  
RTFDS