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TS7003ITD833T 参数 Datasheet PDF下载

TS7003ITD833T图片预览
型号: TS7003ITD833T
PDF下载: 下载PDF文件 查看货源
内容描述: 一个高达300ksps ,单电源, 12位串行输出ADC [A 300ksps, Single-supply, 12-Bit Serial-output ADC]
分类和应用:
文件页数/大小: 14 页 / 963 K
品牌: TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
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TS7003
ELECTRICAL SPECIFICATIONS
V
DD
= +2.7V to +3.6V; f
SCLK
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle, 300ksps; 4.7μF capacitor at
REF; T
A
= -40ºC to +85ºC, unless otherwise noted. Typical values apply at T
A
= +25°C.
PARAMETER
DC ACCURACY
(See Note 1)
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Gain-Error Temperature Coefficient
SYMBOL
CONDITIONS
MIN
12
INL
DNL
ZE
GE
TCGE
See Note 2
No missing codes over temperature
See Note 3
±1.6
70
-80
80
76
10
300
3.3
625
10
< 50
0.5
40
0
10
2.485
2.50
15
30
3
2.515
4.8
60
VREF
±1.0
±1.0
±6.0
±6.0
TYP
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
ppm/°C
dB
dB
dB
dB
MHz
kHz
μs
ns
ns
ps
MHz
%
V
pF
V
mA
ppm/°C
mV/mA
μF
V
V
V
μA
pF
V
V
μA
pF
3.6
1.25
2
±2.5
V
mA
μA
mV
DYNAMIC SPECIFICATIONS
(f
IN
= 75kHz sine wave, 2.5V
PP
, f
SAMPLE
= 300ksps, f
SCLK
= 4.8MHz)
Signal-to-Noise
SINAD
Plus Distortion Ratio
Total Harmonic Distortion
THD
Including the 5th harmonic
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
f
A
= 73kHz, f
B
= 77kHz
Full-Power Bandwidth
FPBW
-3dB point
Full-Linear Bandwidth
FLBW
SINAD > 68dB
CONVERSION RATE
Conversion Time
t
CONV
See Note 4
Track/Hold Acquisition Time
t
ACQ
Aperture Delay
t
AD
Aperture Jitter
t
AJ
Serial Clock Frequency
t
SCLK
Duty Cycle
ANALOG INPUT (AIN)
Input Voltage Range
V
IN
Input Capacitance
C
INA
INTERNAL REFERENCE
REF Output Voltage
VREF
REF Short-Circuit Current
T
A
= +25°C
REF Output Tempco
TCVREF
Load Regulation
See Note 5; 0 to 0.75mA output load
Capacitive Bypass at REF
DIGITAL INPUTS (SCLK,
,
)
Input High Voltage
V
INH
Input Low Voltage
V
INL
Input Hysteresis
V
HYST
Input Leakage
I
IN
V
INL
= 0V or V
INH
= V
DD
Input Capacitance
C
IND
DIGITAL OUTPUT (DOUT)
Output Voltage Low
V
OL
I
SINK
= 5mA
Output Voltage High
V
OH
I
SOURCE
= 0.5mA
Three-State Leakage Current
I
L
V
CS
= +3V
Three-State Output Capacitance
C
OUT
V
CS
= +3V
POWER SUPPLY
Positive Supply Voltage
V
DD
See Note 6
Positive Supply Current
I
DD
See Note 7; V
DD
= +3.6V
Shutdown Supply Current
I
SH
SCLK = V
DD
, SH
= GND
Power-Supply Rejection
PSR
V
DD
= +2.7V to 3.6V, midscale input
4.7
2.4
5
10
0.8
0.2
±1
15
0.4
V
DD
- 0.5
±10
15
2.7
0.95
0.2
±0.5
TS7003DS r1p0
Page 3
RTFDS