TS3002
ELECTRICAL CHARACTERISTICS
V
DD
= 1V, V
CNTRL
= V
DD
, V
BOOST
= 0V, R
SET
= 4.32MΩ, C
SET
= 7.9pF, R
LOAD(FOUT)
= Open Circuit, C
LOAD(FOUT)
= 0pF, C
LOAD(PWM)
= 0pF unless
otherwise noted. Values are at T
A
= 25°C unless otherwise noted. See Note 1.
PARAMETER
Supply Voltage
SYMBOL
V
DD
CONDITIONS
MIN
0.9
-40°C ≤ T
A
≤ 85°C
V
CNTRL
= 0.15 x V
DD
Supply Current
I
DD
V
BOOST
= V
DD
V
BOOST
= V
DD,
V
CNTRL
= 0.15 x V
DD
2.1
-40°C ≤ T
A
≤ 85°C
2.16
-40°C ≤ T
A
≤ 85°C
3.6
-40°C ≤ T
A
≤ 85°C
-40°C ≤ T
A
≤ 85°C
V
BOOST
= V
DD
FOUT Period Line
Regulation
FOUT Period
Temperature Coefficient
Δt
FOUT
/V
Δt
FOUT
/ΔT
1V ≤ V
DD
≤ 1.8V
-40°C ≤ T
A
≤ 85°C
V
BOOST
= V
DD
37
34.7
36
33
40.6
39.5
1.3
-1.6
0.044
0.086
8.9
49.3
90.5
8.5
50.4
91.2
8.6
7.9
0.08
0.3
25
-40°C ≤ T
A
≤ 85°C
(V
DD
- V
CNTRL
), 0.9V < V
DD
< 1.8V
(V
DD
- V
CNTRL
), 0.9V < V
DD
< 1.8V
(V
DD
– V
BOOST
), 0.9V < V
DD
< 1.8V
0.9V < V
DD
< 1.8V
375
131
77
77
10
I
OH
= 1mA
160
45
80
%/V
%/°C
13
54
97
12.5
54
96
TYP
1
1
MAX
1.8
1.5
2.8
3.7
5.4
3.2
4.8
5.3
7.3
44
45.6
43
48
UNITS
V
µA
FOUT Period
t
FOUT
µs
PWMOUT Duty Cycle
DC(PWMOUT)
V
BOOST
= V
DD
V
CNTRL
= 0.03 x V
DD
V
CNTRL
= 0.15 x V
DD
V
CNTRL
= 0.27 x V
DD
V
CNTRL
= 0.03 x V
DD
V
CNTRL
= 0.15 x V
DD
V
CNTRL
= 0.27 x V
DD
See Note 2, C
L
= 15pF
See Note 2, C
L
= 15pF
See Note 3
V
BOOST
= V
DD
4.5
44
83
4.5
47
86
%
FOUT, PWMOUT
Rise Time
FOUT, PWMOUT
Fall Time
FOUT Jitter
RSET Pin Voltage
CNTRL Output Current
PWMOUT Enable
PWMOUT Disable
BOOST Enable
BOOST Disable
BOOST Input Current
High Level Output
Voltage, FOUT and
PWMOUT
Low-level Output
Voltage, FOUT and
PWMOUT
t
RISE
t
FALL
ns
ns
%
V
nA
mV
mV
mV
mV
nA
mV
V(RSET)
I
CNTRL
V
PWM_EN
V
PWM_DIS
V
IH
V
IL
I
BOOST
V
DD
- V
OH
V
OL
I
OL
= 1mA
140
mV
Note 1:
All devices are 100% production tested at T
A
= +25°C and are guaranteed by characterization for T
A
= T
MIN
to T
MAX
, as specified.
Note 2:
Output rise and fall times are measured between the 10% and 90% of the V
DD
power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3:
Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.
TS3002DS r1p0
Page 3
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
