TS3001
ELECTRICAL CHARACTERISTICS
VDD = 1V, VCNTRL = VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF unless otherwise noted. Values are at
TA = 25°C unless otherwise noted. See Note 1.
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
0.9
TYP
1
MAX
1.8
UNITS
V
VDD
1
1.5
-40°C ≤ TA ≤ 85°C
-40°C ≤ TA ≤ 85°C
2.8
3.7
5.4
Supply Current
IDD
µA
µs
2.1
VCNTRL = 0.15 x VDD
38.5
36.8
41.6
44.6
FOUT Period
tFOUT
-40°C ≤ TA ≤ 85°C
FOUT Period Line
Regulation
ΔtFOUT/V
1V ≤ VDD ≤ 1.8V
1.8
%/V
FOUT Period
Temperature Coefficient
ΔtFOUT/ΔT
0.021
%/°C
VCNTRL = 0.03 x VDD
DC(PWMOUT) VCNTRL = 0.15 x VDD
VCNTRL = 0.27 x VDD
6
45
84
10.5
49.8
91
15
54.2
98
PWMOUT Duty Cycle
%
FOUT, PWMOUT
Rise Time
FOUT, PWMOUT
Fall Time
tRISE
tFALL
See Note 2, CL = 15pF
8.6
ns
ns
See Note 2, CL = 15pF
See Note 3
7.9
FOUT Jitter
0.08
%
V
RSET Pin Voltage
V(RSET)
ICNTRL
0.3
25
45
100
CNTRL Output Current
nA
-40°C ≤ TA ≤ 85°C
PWMOUT Enable
PWMOUT Disable
VPWM_EN
VPWM_DIS
(VDD - VCNTRL ), 0.9V < VDD < 1.8V
(VDD - VCNTRL ), 0.9V < VDD < 1.8V
375
mV
mV
131
High Level Output
Voltage, FOUT and
PWMOUT
Low-level Output
Voltage, FOUT and
PWMOUT
VDD - VOH
IOH = 1mA
IOL = 1mA
160
140
mV
mV
VOL
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.
Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.
TS3001DS r1p0
Page 3
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
