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TS3006ITD833T 参数 Datasheet PDF下载

TS3006ITD833T图片预览
型号: TS3006ITD833T
PDF下载: 下载PDF文件 查看货源
内容描述: 一个1.55V至5.25V , 1.9uA , 9kHz到300kHz的硅定时器 [A 1.55V to 5.25V, 1.9uA, 9kHz to 300kHz Silicon Timer]
分类和应用:
文件页数/大小: 9 页 / 641 K
品牌: TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
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TS3006  
To minimize capacitive loading, the technique shown  
in Figure 1 can be used. In this circuit, the principle of  
series-connected capacitors can be used to reduce  
the effective capacitive load at the TS3006’s ꢀOꢁT  
and PWMOUT terminals.  
THEORY OF OPERATION  
The TS3006 is a user-programmable oscillator where  
the period of the square wave at its FOUT terminal is  
generated by an external resistor connected to the  
RSET pin. The output frequency is given by:  
1.0ꢇꢈ11  
ꢀOꢁT ꢂꢃꢄꢅꢆ  ꢀ  
RSꢈT  
Equation 1. FOUT Frequency Calculation  
With an RSET = 4.32M, the output frequency is  
approximately 25kHz with a 50% duty cycle. As  
design aids, Tables 1 lists TS3006’s typical ꢀOꢁT for  
Figure 1: Using an External Capacitor in Series with  
Probes Reduces Effective Capacitive Load.  
various standard values for RSET  
.
To determine the optimal value for CEXT once the  
probe capacitance is known by simply solving for  
CEXT using the following expression:  
RSET (M) FOUT (kHz)  
0.360  
1
300  
108  
1
2.49  
4.32  
6.81  
9.76  
12  
43.37  
25  
15.86  
11.07  
9
CꢈꢉT=  
1
1  
 
CꢊOADꢂꢈꢀꢀꢆ CꢌROꢍꢈ  
Equation 2: External Capacitor Calculation  
Table 1: FOUT vs RSET  
ꢀor example, if the instrument’s input probe  
capacitance is 15pF and the desired effective load  
capacitance at either or both FOUT and PWMOUT  
terminals is to be ≤5pꢀ, then the value of CEXT should  
be ≤7.5pꢀ.  
Connect CPWM to VDD to disable the PWM function  
and in turn, save power. Connect PWM_CNTRL to  
VDD for a fixed PWMOUT output pulse width, which  
is determined by the CPWM pin capacitor only.  
TS3006 Start-up Time  
APPLICATIONS INFORMATION  
As the TS3006 is powered up, its FOUT terminal  
(and PWMOUT terminal, if enabled) is active once  
the applied VDD is higher than 1.55V. Once the  
applied VDD is higher than 1.55V, the master  
oscillator achieves steady-state operation within 8ms.  
Minimizing Power Consumption  
To keep the TS3006’s power consumption low,  
resistive loads at the FOUT and PWMOUT terminals  
increase dc power consumption and therefore should  
be as large as possible. Capacitive loads at the  
FOUT and PWMOUT terminals increase the  
TS3006’s transient power consumption and, as well,  
should be as small as possible.  
One challenge to minimizing the TS3006’s transient  
power consumption is the probe capacitance of  
oscilloscopes and frequency counter instruments.  
Most instruments exhibit an input capacitance of  
15pF or more. Unless buffered, the increase in  
transient load current can be as much as 400nA.  
TS3006DS r1p0  
Page 7  
RTDFS