TS3005 Demo Board
where ICPWM and VCPWM is the current supplied and
voltage applied to the CPWM capacitor, respectively.
The pulse width is determined based on the period of
FOUT and should never be greater than the period at
FOUT. Make sure the PWM_CNTRL pin is set to at
least 400mV when calculating the pulse width of
PWMOUT. Note VCPWM is approximately 300mV,
which is the RSET voltage. Also note that ICPWM is
either 1µA or 100nA. Refer to Table 2 for the output
period range available with a 10MΩ RSET resistor.
DESCRIPTION
The TS3005 requires only an RSET = 10MΩ resistor
to set the FOUT/PWMOUT output period between
47.4ms and 27.6 hours. To change the output period,
an FDIV2:0 combination can be selected. With an on-
board 0.1µF CPWM capacitor, the duty cycle of
PWMOUT is set at approximately 63%. Further
reduction of the duty cycle is available with an on-
board 1MΩ potentiometer. The complete circuit is
designed at a supply voltage of 5V and it is shown in
Figure 1.
FDIV
2:0
ICPWM
(A)
tFOUT
000
001
010
011
100
101
110
111
47.4ms
379.2ms
3.03s
1µ
1µ
The TS3005 is a user-programmable oscillator where
the period of the square wave at its FOUT terminal is
generated by an external resistor connected to the
RSET pin. The output period is given by:
100n
100n
100n
100n
100n
100n
24.26s
3.23min
25.88min
3.451hrs
27.6hrs
8ꢀꢂꢃꢄꢅꢆ0 ꢇ RSET ꢇ 51ꢅ
tꢀOꢁT (s) =
1.08E11
Equation 1. FOUT Frequency Calculation where
Table 2: FOUT and PWMOUT Frequency
Range per FDIV2:0 Combination
for RSET= 10MΩ
FDIV2:0 = 0 to 7
With RSET = 10MΩ and FDIV2:0=000(0), the FOUT
period is approximately 47.4ms with a 50% duty
cycle. As design aids, Tables 1 lists TS3005’s typical
FOUT period for various standard values for RSET and
FDIV2:0 = 111(7).
The PWMOUT output pulse width can be adjusted
further after selecting a CPWM capacitor. This can be
achieved by applying a voltage to the PWM_CNTRL
pin between VRSET and GND. With a voltage of at
least VRSET, the pulse width is set based on
Equation 2. For example, with a period of 47.4ms and
a 0.1µF capacitor at the CPWM pin generates a pulse
width of approximately 30ms. This can be calculated
using Equation 2. By reducing the PWM_CNTRL
voltage from VRSET ꢀ 300mV to GND, the pulse width
can be reduced further. Note that VRSET can be set up
to VDD.
RSET (MΩ)
tFOUT
0.360
1
59.67min
1.09hrs
2.49
4.32
6.81
9.76
12
6.87hrs
11.93hrs
18.81hrs
26.93hrs
33.1hrs
QUICK START PROCEDURE
Required Equipment
Table 1: tFOUT vs RSET for FDIV2:0 = 111(7)
TS3005 Demo Board
The TS3005 also provides a separate PWM output
signal at its PWMOUT terminal that is anti-phase with
respect to FOUT. To adjust the pulse width of the
PWMOUT output, a single capacitor can be placed at
the CPWM pin. To determine the capacitance needed
for a desired pulse width, the following equation is to
be used:
DC Power Supply
Oscilloscope Model Agilent DSO1014A or
equivalent
Two 10X, 15pꢀ//10MΩ oscilloscope probes
Potentiometer screwdriver
Pulse Width(s) ꢇ ꢃCPWM
CPWM(ꢀ)=
ꢄCPWM ꢀ 300mꢄ
Equation 2. CPWM Capacitor Calculation
TS3005DB r1p0
Page 2
RTFDS
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