TS3004
ELECTRICAL CHARACTERISTICS
VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = 47pF, FDIV2:0 = 000 unless
otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1.
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
1.55
TYP
1.9
MAX
5.25
2.4
2.7
3.6
4.5
41.2
42
UNITS
V
VDD
CPWM = VDD
-40°C ≤ TA ≤ 85°C
-40°C ≤ TA ≤ 85°C
Supply Current
IDD
µA
µs
3.3
39
38
40.1
FOUT Period
tFOUT
-40°C ≤ TA ≤ 85°C
FOUT Period Line
Regulation
ΔtFOUT/V
1.55V ≤ VDD ≤ 5.25V
0.17
%/V
%
FOUT Duty cycle
49
51
FOUT Period
Temperature
Coefficient
ΔtFOUT/ΔT
0.02
41.6
%/°C
37
15
48
24
PWMOUT Duty Cycle
DC(PWMOUT)
%
%
VPWM_CNTRL= 0V
PWMOUT Duty Cycle
Line Regulation
ΔDC(PWMOUT)/V 1.55V < VDD < 5.25V, FDIV2:0 = 000
-3
930
810
1050
1150
FDIV2:0 = 000, 001
ICPWM
nA
CPWM Sourcing Current
-40°C ≤ TA ≤ 85°C
FDIV2:0 000, 001
97
nA
UVLO Hysteresis
FOUT, PWMOUT
Rise Time
FOUT, PWMOUT
Fall Time
VUVLO
tRISE
(VDD=1.55V) – (VDD
_
)
150
250
mV
SHUTDOWN VOLTAGE
See Note 2, CL = 15pF
10
10
ns
ns
tFALL
See Note 2, CL = 15pF
See Note 3
FOUT Jitter
0.001
0.3
%
V
RSET Pin Voltage
V(RSET)
IFDIV
10
20
nA
FDIV Input Current
-40°C ≤ TA ≤ 85°C
Maximum Oscillator
Frequency
High Level Output
Voltage, FOUT and
PWMOUT
Fosc
RSET= 360K
IOH = 1mA
300
kHz
mV
VDD - VOH
160
Low Level Output
Voltage, FOUT and
PWMOUT
VOL
TDT
IOL = 1mA
140
106
mV
ns
Dead Time
FOUT edge falling and PWMOUT edge rising
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.
Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.
TS3004DS r1p0
Page 3
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
