TS12011/TS12012
ELECTRICAL CHARACTERISTICS
V
DD
= 0.8V; V
SS
= 0V; V
COMPIN+/-
= 0V; V
AMPIN+/-
= 0V; V
AMPOUT
= (V
DD
+ V
SS
)/2; V
COMPOUT
= HiZ; T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C. See note 1.
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
DD
0.8
2.5
V
T
A
= +25°C
1.1
1.6
Supply Current
I
DD
REFOUT = open
µA
-40°C ≤ T
A
≤ 85°C
2
REFERENCE SECTION
T
A
= +25°C
555
577
600
Reference Output
V
REFOUT
mV
Voltage
-40°C ≤ T
A
≤ 85°C
552
602
Reference Load
I
OUT
= ±100nA
0.5
%
Regulation
AMPLIFIER SECTION
T
A
= +25°C
3.5
mV
Input Offset Voltage
V
OS
V
AMPIN+/-
= V
DD
or V
AMPIN+/-
= V
SS
-40°C ≤ T
A
≤ 85°C
7
Input Bias Current
Input Offset Current
Input Common-Mode
Range
Large-Signal Voltage
Gain
Gain-Bandwidth
Product
Phase Margin
Slew Rate
Common-Mode
Rejection Ratio
Power-Supply
Rejection Ratio
Output High Voltage
Output Low Voltage
Output Source
Current
Output Sink Current
Output Load
Capacitive Drive
Input Offset Voltage
Input Hysteresis
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode
Rejection Ratio
Power-Supply
Rejection Ratio
Low-to-High
Propagation Delay
High-to-Low
Propagation Delay
Output High Voltage
Output Low Voltage
Output Low Voltage
Output Short-Circuit
Current
Open Drain Leakage
I
IN+
, I
N-
I
OS
IVR
A
VOL
GBWP
φ
M
SR
CMRR
PSRR
V
OH
V
OL
I
SC+
I
SC-
C
OUT
COMPARATOR SECTION
T
A
= +25°C
V
AMPIN+/-
= V
DD
; V
AMPIN+/-
= V
SS
;
See Note 2
-40°C ≤ T
A
≤ 85°C
See Note 3
V
COMPIN+,
V
COMPIN-
= V
DD
or V
SS
V
COMPIN+,
V
COMPIN-
= V
DD
or V
SS
Guaranteed by Input Offset Voltage Test
0V ≤ V
IN(CM)
≤ 2.1V; V
DD
= 2.5V
0.8V ≤ (V
DD
- V
SS
) ≤ 2.5V
V
OVERDRIVE
= 10mV; See Note 4
TS12011
V
OVERDRIVE
= 100mV; See Note 4
V
OVERDRIVE
= 10mV; See Note 4
V
OVERDRIVE
= 100mV; See Note 4
TS12011; I
OUT
= -100μA
TS12011 ; I
OUT
= 100μA
TS12012 ; I
OUT
= 100μA
Sourcing; V
COMPOUT
= V
SS
TS12011 ; Sinking; V
COMPOUT
= V
DD
TS12012 ; Sinking; V
COMPOUT
= V
DD
TS12012 ; V
COMPOUT
= 5V
V
AMPIN+,
V
AMPIN-
= (V
DD
– V
SS
)/2
V
AMPIN+,
V
AMPIN-
= (V
DD
– V
SS
)/2
Guaranteed by Input Offset Voltage Test
R
L
= 100K to V
DD
/2;
V
SS
+ 50mV < V
OUT
< V
DD
- 50mV
R
L
= 100kΩ//20pF
R
L
= 100kΩ//20pF
R
L
= 100kΩ//20pF
0V ≤ V
IN(CM)
≤ 2.1V; V
DD
= 2.5V
0.65V ≤ (V
DD
- V
SS
) ≤ 2.5V
R
L
= 100kΩ to V
SS
R
L
= 100kΩ to V
DD
V
AMPOUT
= V
SS
V
AMPOUT
= V
DD
50
50
V
DD
– 50mV
V
SS
+ 50mV
0.28
4.5
50
4.5
8
±7.5
0.2
V
SS
50
50
60
70
30
20
30
20
V
DD
– 0.1
V
SS
+ 0.1
V
SS
+ 0.11
0.1
0.5
1.4
20
20
5
V
DD
V
SS
90
104
15
70
6
75
75
0.01
20
5
V
DD
nA
nA
V
dB
kHz
deg
V/ms
dB
dB
V
V
mA
mA
pF
mV
mV
nA
nA
V
dB
dB
µs
µs
µs
µs
V
V
V
mA
mA
mA
nA
V
OS
V
HB
I
IN+
, I
N-
I
OS
IVR
CMRR
PSRR
t
PD+
t
PD-
V
OH
V
OL
V
OL
I
SC
TS12011_12DS r1p0
Page 3
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
