TS1001
Configuring the TS1001 as Nanowatt Analog
Comparator
of an analog comparator using the TS1001 should
also use as little current as practical. The first step in
the design, therefore, was to set the feedback
resistor R3:
Although optimized for use as an operational
amplifier, the TS1001 can also be used as a rail-to-
rail I/O comparator as illustrated in Figure 7.
R3 = 10Mꢀ
Calculating a value for R1 is given by the following
expression:
R1 = R3 x (VHYB/VDD)
Substituting VHYB = 100mV, VDD = 1.5V, and R3 =
10Mꢀ into the equation above yields:
R1 = 667kꢀ
Figure 7: A NanoWatt Analog Comparator with User-
The following expression was then used to calculate
a value for R2:
Programmable Hysteresis.
External hysteresis can be employed to minimize the
risk of output oscillation. The positive feedback
circuit causes the input threshold to change when
the output voltage changes state. The diagram in
Figure 8 illustrates the TS1001’s analog comparator
R2 = 1/[VHI/(VREF x R1) – (1/R1) – (1/R3)]
Substituting VHI = 1V, VREF = 0.75V, R1 = 667kꢀ,
and R3 = 10Mꢀ into the above expression yields:
R2 = 2.5Mꢀ
Printed Circuit Board Layout Considerations
Even though the TS1001 operates from a single
0.65V to 2.5V power supply and consumes very little
supply current, it is always good engineering
practice to bypass the power supplies with a 0.1μF
ceramic capacitor placed in close proximity to the
Figure 8: Analog Comparator Hysteresis Band and Output
Switching Points.
hysteresis band and output transfer characteristic.
VDD and VSS (or GND) pins.
The design of an analog comparator using the
TS1001 is straightforward. In this application, a 1.5-
V power supply (VDD) was used and the resistor
divider network formed by RD1 and RD2 generated
a convenient reference voltage (VREF) for the circuit
at ½ the supply voltage, or 0.75V, while keeping the
current drawn by this resistor divider low. Capacitor
C1 is used to filter any extraneous noise that could
couple into the TS1001’s inverting input.
Good pcb layout techniques and analog ground
plane management improve the performance of any
analog circuit by decreasing the amount of stray
capacitance that could be introduced at the op amp's
inputs and outputs. Excess stray capacitance can
easily couple noise into the input leads of the op
amp and excess stray capacitance at the output will
add to any external capacitive load. Therefore, PC
board trace lengths and external component leads
should be kept a short as practical to any of the
TS1001’s package pins. Second, it is also good
engineering practice to route/remove any analog
ground plane from the inputs and the output pins of
the TS1001.
In this application, the desired hysteresis band was
set to 100mV (VHYB) with a desired high trip-point
(VHI) set at 1V and a desired low trip-point (VLO) set
at 0.9V.
Since the TS1001 is a very low supply current
amplifier (0.6µA, typical), it is desired that the design
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TS1001DS r1p0
RTFDS
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