TC55VEM316AXGN40,55
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
Lead-Free
The TC55VEM316AXGN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7
µA
standby
current (at V
DD
=
3 V, Ta
=
25°C, typical) when chip enable (
CE1
) is asserted high or (CE2) is asserted low. There
are three control inputs.
CE1
and CE2 are used to select the device and for data retention control, and output
enable (
OE
) provides fast memory access. Data byte control pin (
LB ,
UB
) provides lower and upper byte access.
This device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. And, with a guaranteed operating extreme temperature range of
−
40° to 85°C, the
TC55VEM316AXGN can be used in environments exhibiting extreme temperature conditions. The
TC55VEM316AXGN is available in a plastic 48-ball BGA.
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using
CE1
and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−
40° to 85°C
Standby Current (maximum):
3.6 V
3.0 V
10
µA
5
µA
•
Access Times:
TC55VEM316AXGN
40
Access Time
CE1 Access Time
CE2
OE
Access Time
Access Time
40 ns
40 ns
40 ns
25 ns
55
55 ns
55 ns
55 ns
30 ns
•
•
Package:
P-TFBGA48-0811-0.75BZ (Weight: 0.157 g typ)
Lead-Free
PIN ASSIGNMENT
(TOP VIEW)
48 PIN BGA
1
A
B
LB
I/O9
2
OE
UB
3
A0
A3
A5
A17
OP
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
I/O2
I/O4
I/O5
I/O6
R/W
A11
6
CE2
I/O1
I/O3
V
DD
V
SS
I/O7
I/O8
NC
PIN NAMES
A0~A18
Address Inputs
CE1 , CE2
R/W
OE
LB , UB
I/O1~I/O16
D
E
V
SS
V
DD
I/O12
I/O13
V
DD
GND
NC
OP*
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Option
C I/O10 I/O11
F I/O15 I/O14
G I/O16
H
A18
NC
A8
*
: OP pin must be open or connected to GND.
2004-01-28
1/14
TOSHIBA [ TOSHIBA SEMICONDUCTOR ]
