6N135,6N136
Switching Specifications
(unless otherwise specified. Ta = 25°C, V
CC
= 5V, I
F
= 16mA)
Characteristic
Propagation delay
time to logic low
at output
Propagation delay
time to logic high
at output
Common mode
transient immunity
at logic high level
output
(Note 10)
6N135
6N136
6N135
6N136
6N135
CM
H
6N136
2
Symbol
t
pHL
Test
Circuit
1
Test Condition
R
L
= 4.1kΩ
R
L
= 1.9kΩ
R
L
= 4.1kΩ
R
L
= 1.9kΩ
I
F
= 0mA
V
CM
= 10V
p−p
R
L
= 4.1kΩ
I
F
= 0mA
V
CM
= 10V
p−p
R
L
= 1.9kΩ
V
CM
= 10V
p−p
R
L
= 4.1kΩ
I
F
= 16mA
V
CM
= 10V
p−p
R
L
= 1.9kΩ
I
F
= 16mA
R
L
= 100Ω
Min.
―
―
―
―
―
Typ.
0.2
0.2
1.0
0.5
1000
Max.
1.5
0.8
1.5
0.8
―
Unit
μs
μs
μs
μs
V /
μs
t
pLH
1
―
1000
―
V /
μs
Common mode
transient immunity
at logic low level
output
(Note 10)
Bandwidth
6N135
CM
L
6N136
(Note 11)
BW
―
2
―
−1000
―
V /
μs
―
―
−1000
2
―
―
V /
μs
MHz
(Note 8)
(Note 9)
(Note 10)
(Note 11)
DC current transfer ratio is defined as the ratio of output collector current, I
O
, to the forward LED
input current, I
F
, times 100%.
Device considered a two−terminal device: Pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7 and 8
shorted together.
Common mode transient immunity in logic high level is the maximum tolerable (positive) dv
CM
/ dt on
the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a logic high
state (i.e., V
O
> 2.0V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dv
CM
/ dt on
the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic
low state (i.e., V
O
< 0.8V).
The frequency at which the AC output voltage is 3dB below the low frequency asymptote.
4
2007-10-01
TOSHIBA [ TOSHIBA SEMICONDUCTOR ]
