04S_01XC9101/9102新規 02.09.12 14:38 ページ 400
XC9101Series
ꢀRecommended Pattern Layout
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In order to stablize VDD's voltage level, we recommend that a by-pass capacitor (CDD) be connected as close as possible to the VIN & VSS
pins.
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In order to stablize the GND voltage level which can fluctuate as a result of switching, we suggest that C_CLK's, R_CLK's & C_GAIN's GND
be separated from Power GND and connected as close as possible to the VSS pin (by-pass capacitor, CDD). Please use a multi layer board
and check the wiring carefully.
Pattern Layout Examples
XC9101D Series
2 Layer Evaluation Board
L
SD
CDD
4
CFB
N-MOS
RFB1
VDD Line
5
1
CL
IC GND
6
7
2
RSEN
3
Power GND
RFB2
R_SS
C_GAIN
CIN
8
R_CLK
4
VIN
C_SS
C_CLK
Through Hole
1
2
3
4
5
6
7
8
R_CLK, C_CLK, C_GAIN, RFB2ꢀ�
GND
Through Hole
400
TOREX [ Torex Semiconductor ]
