XC61H
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
An input voltage V
IN
starts higher than the release voltage V
DR
. Then, V
IN
voltage will gradually fall. When V
IN
voltage is
higher than detect voltage V
DF
, output voltage RESETB is equal to the V
IN
voltage.
*Note that high impedance exists at RESETB with the N-channel open drain configuration. If the RESETB pin is pulled
up, RESETB will be equal to the pull up voltage.
②
When V
IN
falls below V
DF
, RESETB will be equal to ground voltage V
SS
level (detect state).
* Note that this also applies to N-channel open drain configurations.
③
When VI
N
falls to a level below that of the minimum operating voltage V
MIN,
output will become unstable.
*When the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
④
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), RESETB will be equal to
V
SS
until V
IN
reaches the V
DR
level.
⑤
Although V
IN
will rise to a level higher than V
DR
, RESETB maintains ground voltage level via the delay circuit.
⑥
After taking a release delay time, V
IN
voltage will be output at the RESETB pin.
*High impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
①
Notes:
1. The difference between V
DR
and V
DF
represents the hysteresis width.
2. Release delay time (
t
DR
) represents the time it takes until when V
IN
voltage appears at RESETB pin once the input
voltage has exceeded the V
DR
level.
●Timing
Chart
Output Voltage (RESETB)
Release Delay Time (t
DR
)
5/13
TOREX [ TOREX SEMICONDUCTOR ]
