XC61H
Series
■OPERATIONAL EXPLANATION
●CMOS output
①
An input voltage VIN starts higher than the release voltage VDR. Then, VIN voltage will gradually fall. When VIN voltage is
higher than detect voltage VDF, output voltage RESETB is equal to the VIN voltage.
*Note that high impedance exists at RESETB with the N-channel open drain configuration. If the RESETB pin is pulled
up, RESETB will be equal to the pull up voltage.
②
③
When VIN falls below VDF, RESETB will be equal to ground voltage VSS level (detect state).
* Note that this also applies to N-channel open drain configurations.
When VIN falls to a level below that of the minimum operating voltage VMIN, output will become unstable.
*When the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
④
When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), RESETB will be equal to
VSS until VIN reaches the VDR level.
⑤
⑥
Although VIN will rise to a level higher than VDR, RESETB maintains ground voltage level via the delay circuit.
After taking a release delay time, VIN voltage will be output at the RESETB pin.
*High impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
Notes:
1. The difference between VDR and VDF represents the hysteresis width.
2. Release delay time (tDR) represents the time it takes until when VIN voltage appears at RESETB pin once the input
voltage has exceeded the VDR level.
●Timing Chart
Output Voltage (RESETB)
Release Delay Time (tDR
)
5/13
TOREX [ Torex Semiconductor ]
