XC61F
Series
■MARKING
RULE
●SOT-23,
SOT-89
3
① ② ③ ④
1
2
1
2
3
①Represents
integer of detect voltage and output configuration
CMOS output (XC61FC series)
MARK
CONFIGURATION
VOLTAGE (V)
A
CMOS
0.x
B
CMOS
1.x
C
CMOS
2.x
D
CMOS
3.x
E
CMOS
4.x
F
CMOS
5.x
H
CMOS
6.x
N-channel open drain (XC61FN series)
MARK
CONFIGURATION
VOLTAGE (V)
K
N-ch
0.x
L
N-ch
1.x
M
N-ch
2.x
N
N-ch
3.x
P
N-ch
4.x
R
N-ch
5.x
S
N-ch
6.x
②Represents
decimal number of detect voltage
MARK
VOLTAGE (V)
MARK
0
x.0
5
1
x.1
6
2
x.2
7
3
x.3
8
4
x.4
9
③Represents
delay time
VOLTAGE (V)
5
6
7
VOLTAGE (V)
x.5
x.6
x.7
x.8
x.9
DELAY TIME
50 ~ 200ms
80 ~ 400ms
1 ~ 50ms
②
①
③
④
④Represents
assembly lot number (Based on internal standards)
●TO-92
①Represents
output configuration
MARK
C
N
②, ③Represents
detect voltage
MARK
②
3
5
④Represents
delay time
MARK
1
4
5
⑤Represents
detect voltage accuracy
MARK
2
OUTPUT CONFIGURATION
CMOS
N-ch
③
3
0
VOLTAGE (V)
3.3
5.0
DELAY TIME
50ms ~ 200ms
80ms ~ 400ms
1ms ~ 50ms
DETECT VOLTAGE ACCURACY
Within +2%
⑥Represents
a least significant digit of the production year (ex.)
MARK
PRODUCTION YEAR
3
2003
4
2004
⑦Represents
production lot number
0 to 9, A to Z repeated (G, I, J, O, Q, W expected)
11/12
TOREX [ TOREX SEMICONDUCTOR ]
