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XC221A1100MR 参数 Datasheet PDF下载

XC221A1100MR图片预览
型号: XC221A1100MR
PDF下载: 下载PDF文件 查看货源
内容描述: 1.2V输入/输出轨至轨CMOS运算放大器 [1.2V Input / Output Rail To Rail CMOS Op Amp]
分类和应用: 运算放大器
文件页数/大小: 8 页 / 190 K
品牌: TOREX [ TOREX SEMICONDUCTOR ]
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Series
PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits (For Low Frequency range)
NCMOS
Low Power Consumption
NInput
Frequency
NDivider
Ratio
NMultiplier
Ratio
: 12KHz to 35MHz
: 1, 3 ~ 2047 divisions
■Applications
GCrystal
Oscillation Modules
GPersonal
Computers
GPDAs
1
(laser trimming)
GPortable
Audio Systems
: 6 ~ 2047 multiplications
GVarious
System Clocks
(laser trimming)
NComparative
Frequency : 12KHz ~ 500KHz
NOutput
Frequency : 3MHz ~ 30MHz
NMini
Mold SOT-26 Package
■General Description
The XC25BS5 series are high frequency, low power consumption PLL
clock generator ICs with divider circuit & multiplier PLL circuit.
Laser trimming gives the option of being able to select from divider ratios
(M) of 1,3 to 2047 and multiplier ratios (N) of 6 to 2047.
Output frequency (Q0) is equal to reference oscillation (fCLKin)
multiplied by N/M, within a range of 3MHz to 30MHz. Q1 output is
selectable from input reference frequency (f0), input reference
frequency/2 (f0/2), ground (GND), and comparative frequency (f0/M).
Further, comparative frequencies, within a range of 12KHz to 500KHz,
can be obtained by dividing the reference oscillation. By halting
operation via the CE pin, consumption current can be controlled and
output will be one of high-impedance.
■Features
Output Frequency
: 3MHz ~ 30MHz (Q0=fCLKin
×
N/M)
Reference Oscillation (fCLKin)
: 12KHz ~ 35MHz
Divider Ratio (M)
Multiplier Ratio (N)
Output
: Selectable from divisions of 1, 3 ~ 2047
: Selectable from multiplications of 6 ~ 2047
: 3-State
Q1 output selectable from input reference
oscillation, input reference oscillation/2,
GND, comparative frequency.
Operating Voltage Range:
2.97V ~ 5.5V
Low Power Consumption
: CMOS (stand-by function included)*1
Ultra Small Package
: SOT-26 mini mold
*1 High output impedance during standby
■Pin Configuration
CE
V
SS
Q
0
1
■ Pin Assignment
PIN NUMBER PIN NAME
CE
V
SS
Q
0
Q
1
V
DD
CLKin
FUNCTION
Chip Enable
GND
PLL Output
Reference Oscillation, Reference
Oscillation/2, GND, or Comparative
Frequency Output
Power Supply
Reference Clock Input
CLK
in
V
DD
Q
1
SOT-26
(TOP VIEW)
■Function List
GCE,
Q0/Q1 Pin Function
CE
"H"
"L"
Open
FUNCTION
Q
0
, Q
1
clock output
Standby. Ouput pin = high impedance
Standby. Ouput pin = high impedance
(V
SS
pin pull down due to IC's internal resistor)
"H" = High level
"L" = Low level
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